专利摘要:
A distributed control digital switching network is configured as a group switch having a plurality of stages of multiport single sided switching elements for selectively interconnecting a plurality of input terminals via the transmission paths established through the network by path selection control signals which are multiplexed on common transmission links to and through the network together with digitally encoded data from the terminals on common transmission paths such that data is received phase asynchronously at each stage of the network and is either coupled to a higher order stage of the network or folded back through the network by reflection to interconnect terminals switched by the network. The single-sided switching elements are selectively operable as single-sided or multi-sided in accordance with their position in the network.
公开号:SU1321383A3
申请号:SU792738610
申请日:1979-03-16
公开日:1987-06-30
发明作者:Джеймс Лоренс Алан;Майкл Коттон Джон;Нейл Дененберг Джеффри
申请人:Интернэшнл Стандарт Электрик Корпорейшн (Фирма);
IPC主号:
专利说明:

13
The invention relates to the transmission of digital information between subscribers of the telephone network, between computers and other sources of digital signals.
The purpose of the invention is to increase throughput.
The drawing shows a structural electrical circuit of the proposed digital switching device.
The digital switching device contains an input synchronizer I, a buffer register 2, a reception control block 3, a common bus 4, a decoder 5, a data memory block 6, an output register 7, a transmission synchronization block 8, a block of receiving reception failure signals, a control block 10 transmission block 11 of the transmission control memory, block 12 of the channel memory, block 13 of the reception control memory, block 14 of selecting the free address, block 15 of the address memory, block 16 of searching for the free channel, block 17 of searching for the negative acknowledgment sign, block 18 of entering the signal failure before chi.
The device works as follows.
Input synchronizer 1 provides clock and cycle synchronization. The output signal from input synchronizer 1 is a 16-bit channel word and the signals that determine the channel number (representing the channel position in the frame). The buffer register 2 provides synchronization of information from the output of the synchronizer 1 with the clocking of the common bus 4. The output signal of the buffer register 2 is a 16-bit channel word and 5-bit channel number. In the protocol bits the 16-bit channel word contains information that together with the information contained in block 13, determines the action that should be taken by block 3 for the given channel in this frame. There are five possible actions: Spata, Select, Query, Replace, Erase. If the protocol is Spata (voice and information signals), the channel word is sent to the common bus 4 unchanged and from the I2 and 15 block the direction and channel addresses are selected that are sent to the common bus 4. If the select command is 32
c Any direction, Any channel, block 14 defines the transmission logic for the Select First Free Channel command.
On the common bus 4 access interval to the receiving part, the selection of the first free channel in the selected direction is performed with the return of the Free channel number from block 16.
Block 9 angles the channel information to indicate failure to establish communications from other digital switching devices and excludes channel numbers with the symbol
refusal of admission.
If the encoder 5 decodes the exact direction address, and the shared bus 4 selection line is inactive, the contents of the Spata lines of the common bus 302 will be
rewritten in block 6 with the address specified by the state of the line of addresses of the channels of the shared bus 4 ,.
If the line selects a common tire 4
is active, and block 3 requests a search for the first free channel and then no information is recorded in block 16, and the number of the free channel returns to block 13 from
block 16. Block 6 is an exchange device for a time interval and information is fed to it sequentially (as read) in accordance with the operation of block 8.
The words read from block 6 are transmitted in parallel to the output register 7, from where they sequentially arrive on the line as a sequence of binary bits. .
Block 11 stores the state of each outgoing channel and inserts them into block 10, which manages the writing and reading of information in block 6 and the operation of block 10 and output register 7.
权利要求:
Claims (1)
[1]
Invention Formula
Digital switching device.
BOj containing a serially connected input synchronizer, a buffer register and a reception control unit, the first output of which is connected to the common bus, as well as a serially connected decoder and memory unit, the output of which is connected to the output register, as well as a reception control memory connected to the reception control unit, the second
313213834
the output of which is connected to the common wifi is connected to the output of the selection block of its own, to which the output of the block address is connected, the input of which and the transmission synchronization and the input of the de-address of the memory block of the address are connected to the encoder the bus, which is connected to the second, to increase the throughput, eye and third inputs of the capacity storage unit, is inserted into the serial data and the input and output of the search unit — the connected receive unit of signals from a free channel, control over the transfer ohm is connected through the dacha and the memory unit of the re-sequentially connected feed unit, as well as the channel memory unit, the search: negative acknowledgment sign — the first input and output of which is the connection and the input unit of the failure signals with the common bus and the second the input of the sub-transmission with an additional input is turned off to the third output of the control register block, and the output of the reception block by the reception, the fourth output of which signals the refusal from receiving one is connected to the first input of the 15din block with the output of the buffer register addresses, second entrance which
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同族专利:
公开号 | 公开日
AU526568B2|1983-01-20|
GB2029671A|1980-03-19|
CA1127279A|1982-07-06|
NO790849L|1979-09-18|
IN151836B|1983-08-13|
HK14084A|1984-02-24|
TR20713A|1982-05-21|
PL214208A1|1980-05-05|
FI74861C|1988-03-10|
SG68083G|1984-08-03|
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ES478735A1|1980-07-16|
GB2016865A|1979-09-26|
YU41854B|1988-02-29|
HK19284A|1984-03-16|
MX150747A|1984-07-11|
NL190859B|1994-04-18|
IT7920994D0|1979-03-15|
SE7902268L|1979-09-18|
FI790837A|1979-09-18|
DK156320B|1989-07-31|
SG67983G|1985-01-11|
FR2420263B1|1986-12-26|
NZ189851A|1982-08-17|
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BR7901671A|1979-10-16|
SE442804B|1986-01-27|
GR66566B|1981-03-27|
HU180481B|1983-03-28|
PT69348A|1979-04-01|
FR2420263A1|1979-10-12|
GB2029671B|1982-09-22|
DK108279A|1979-09-18|
AU4501479A|1979-09-20|
YU65279A|1982-10-31|
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IT1192698B|1988-05-04|
JPS6243600B2|1987-09-16|
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法律状态:
优先权:
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